This application is based on applications Nos. H9-234354 and H10-095645 filed in Japan, the content of which is hereby incorporated by reference.
1. Field of the Invention
The present invention relates to a processor and an instruction conversion apparatus, and in particular to a technique for reducing the number of types of instructions and the processor hardware scale when conditional instructions are used.
2. Related Art
In recent years, improvements in performance and processing speed of appliances using embedded microprocessors have led to an in creasing demand for microprocessors (hereinafter simply referred to as xe2x80x9cprocessorsxe2x80x9d) with high processing capability.
A basic technique for increasing processing speed is a pipeline processing.
In the pipeline processing, the processing of each instruction is divided into a plurality of processing units (pipeline stages) and pipeline stages for different instructions are executed in parallel so that processing speed is improved.
The pipeline processing is disturbed, however, (pipeline stalls occur) when executing a branch, reducing the execution performance of the pipelines to below an ideal level. This phenomenon is called a xe2x80x9cbranch hazardxe2x80x9d.
Recent processors use conditional instructions instead of branch instructions to reduce branch hazards to improve their processing capabilities. The conditional instructions are, for instance, described in detail in xe2x80x9cThe ARM RISC Chip-A Programmer""s Guidexe2x80x9d, Addison-Wesly Publishing Company Inc.
FIG. 30 shows an instruction sequence including a conventional conditional transfer instruction. In FIG. 30, each of the legends xe2x80x9cr0xe2x80x9d, xe2x80x9cr1xe2x80x9d, and xe2x80x9cr2xe2x80x9d represents a register. The instruction 3001 is a transfer instruction for transferring the value xe2x80x9c1xe2x80x9d to the register xe2x80x9cr0xe2x80x9d. The instruction 3002 is a comparison instruction for comparing the values of the registers xe2x80x9cr1xe2x80x9d and xe2x80x9cr2xe2x80x9d and setting various flags to indicate the comparison result. The instruction 3003 is a conditional transfer instruction for referring to the flags and, when the values compared by the instruction 3002 are equal, transferring the value xe2x80x9c0xe2x80x9d to the register xe2x80x9cr0xe2x80x9d.
FIG. 31 shows a list of conventional conditional transfer instructions 3101. This list includes six types of conditional transfer instructions 3101. The condition 3102 is a sign indicating a condition specified by each conditional transfer instruction. When the operation objects xe2x80x9caxe2x80x9d and xe2x80x9cbxe2x80x9d are compared by a comparison instruction, the condition is one of the following cases: xe2x80x9caxe2x80x9d and xe2x80x9cbxe2x80x9d are equal; xe2x80x9caxe2x80x9d and xe2x80x9cbxe2x80x9d are not equal; xe2x80x9caxe2x80x9d is greater than xe2x80x9cbxe2x80x9d; xe2x80x9caxe2x80x9d is greater than or equal to xe2x80x9cbxe2x80x9d; xe2x80x9caxe2x80x9d is smaller than xe2x80x9cbxe2x80x9d; and xe2x80x9caxe2x80x9d is smaller than or equal to xe2x80x9cbxe2x80x9d. Each conditional transfer instruction is executed when its condition is satisfied.
FIG. 32 shows conventional instructions, such as comparison instructions (CMP instructions), conditional addition instructions for performing addition when their conditions are satisfied, conditional transfer instructions for performing transfer when their conditions are satisfied, and conditional branch instructions for performing branch when their conditions are satisfied. In these instructions, last two characters of the operation code of each instruction in mnemonic code specify the condition.
The number of types of conditions of each conditional instruction and each conditional branch instruction shown in FIG. 32 is ten because the conditions shown in FIG. 32 include conditions for data with signs, in addition to the conditions shown in FIG. 31.
Accordingly, the total number of types of instructions including a comparison instruction, conditional instructions for each of two operations (conditional transfer instructions and conditional addition instructions), and conditional branch instructions is thirty-one. Here, if there are A operations of conditional instructions, the total number is represented as 11+(10xc3x97A).
There are also conditional instructions whose number of types is reduced. These conditional instructions are described in detail in xe2x80x9cHitachi Single Chip RISC Microcomputer SH7000/SH7600 Series Programming Manualxe2x80x9d, Hitachi, Ltd., p57-p58, p69-p70, and p75-p78.
FIG. 33 shows comparison instructions, conditional addition instructions, and conditional branch instructions where the number of instruction types is reduced.
Here, the conditional instructions and the conditional branch instructions shown in FIG. 33 use only two types of conditions, that is, a conditional flag is set or is reset. Therefore, FIG. 33 shows two types of conditional addition instructions, two types of conditional transfer instructions, two types of conditional branch instructions, and five types of comparison instructions for setting or resetting the conditional flag.
Accordingly, the total number of types of instructions including comparison instructions, conditional instructions for each of two operations, and conditional branch instructions is eleven. Here, if there are A types of operations of conditional instructions, the total number of types of instructions including comparison instructions, conditional instructions for each operation, and conditional branch instructions is represented as 7+(2xc3x97A).
Processors performing pipeline processing need to use more types of conditional instructions to reduce branch hazards as much as possible.
However, because each instruction executed by a processor has a fixed-length bit pattern, the number of types of instructions which the processor can use is limited.
Accordingly, the number of types of conditional instructions which the processor can use is limited. As the number of types of instructions increases, more hardware is required to decode instructions, increasing the cost of the processor.
In view of the stated problems, the object of the present invention is to provide an instruction conversion apparatus which reduces the number of types of instructions and a processor whose hardware scale is reduced, when conditional instructions are used.
To achieve the above object, the processor of the present invention which decodes and executes an instruction sequence includes: a state hold unit for holding, when a predetermined instruction is executed, a renewal state for an execution result of the predetermined instruction; an obtaining unit for obtaining an instruction sequence composed of instructions matching instructions assigned to an instruction set of the processor, where the instruction set is assigned first conditional instructions, a first state condition for a first conditional instruction being mutually exclusive with a second state condition for a second conditional instruction which has a same operation code as the first conditional instruction, the instruction set not being assigned the second conditional instruction, and the first state condition and the second state condition specifying either of one state and a plurality of states; a decoding unit for decoding each instruction in the obtained instruction sequence one by one; a judging unit for judging whether the renewal state is included in either of the state and the plurality of states specified by the first state condition in the first conditional instruction, when the decoding unit decodes the first conditional instruction; and an execution unit for executing, only if a judgement result by the judging unit is affirmative, an operation specified by the operation code in the first conditional instruction decoded by the decoding unit.
With the stated construction, the processor of the present invention uses an instruction set including only conditional instructions specifying one out of a pair of exclusive conditions, not including conditional instructions specifying the other of the pair. Therefore, the number of types of conditional instructions is reduced, in comparison with a conventional processor.
Accordingly, hardware scale of an instruction decoder can be reduced. Also, when the number of types of instructions is limited, the processor of the present invention can be provided with conditional instructions of more operations. As a result, when the processor of the present invention performs pipeline processing, branch hazards can be reduced.
Here, the renewal state may show a relation between magnitudes of two comparison objects a and b, the relation corresponding to an execution result of a type of comparison instruction, where execution of a first conditional instruction is only possible after a comparison instruction, and the instruction set is assigned three types of first conditional instructions, the first condition states of the three types of first conditional instructions being: 1. one out of xe2x80x9ca=bxe2x80x9d and xe2x80x9caxe2x89xa0bxe2x80x9d; 2. one out of xe2x80x9caxe2x89xa7bxe2x80x9d and xe2x80x9ca less than bxe2x80x9d; and 3. one out of xe2x80x9caxe2x89xa6bxe2x80x9d and xe2x80x9ca greater than bxe2x80x9d.
With the stated construction, the processor of the present invention uses three types of conditional instructions for each operation, so that the number of types of conditional instructions can be reduced by half of that of a conventional processor.
Therefore, hardware scale of an instruction decoder can be reduced. Also, when the number of types of instructions is limited, the number of types of conditional instructions can be increased by twice of that of a conventional processor. Therefore, when the processor of the present invention performs pipeline processing, branch hazards can be reduced.
Here, an operation code included in a conditional instruction may be one of a transfer operation code, an arithmetic operation code, and a logic operation code.
With the stated construction, the operation of each conditional instruction included in the instruction set of the processor of the present invention is a transfer operation, an arithmetic operation, and a logic operation.
Therefore, the processor of the present invention can use conditional transfer instructions, conditional arithmetic instructions, and conditional logic instructions. Accordingly, when the processor of the present invention performs pipeline processing, branch hazards can be reduced.
To achieve the above object, the processor of the present invention which decodes and executes an instruction sequence includes: an obtaining unit for obtaining an instruction sequence composed of instructions matching instructions assigned to an instruction set of the processor, where the instruction set is assigned at least one first conditional flag setting instruction, at least one second conditional flag setting instruction, and at least one conditional execution instruction, each first conditional flag setting instruction including a first condition, and each second conditional flag setting instruction including a second condition, each first condition being mutually exclusive with one of the second conditions, each conditional execution instruction including an operation code that is not included in any other conditional execution instruction in the instruction set; a decoding unit for decoding each instruction in the obtained instruction sequence one by one; a conditional flag for holding a judgement result as to whether a predetermined condition is satisfied; a judging unit for judging, when the decoding unit decodes the first conditional flag setting instruction, whether the first condition in the first conditional flag setting instruction is satisfied and has the conditional flag hold a judgement result for the first condition and, when the decoding unit decodes the second conditional flag setting instruction, judges whether the second condition in the second conditional flag setting instruction is satisfied and has the conditional flag hold a judgement result for the second condition; and an execution unit for executing, only if the decoding unit decodes the conditional execution instruction and the judgement result held by the conditional flag indicates that a condition for the conditional execution instruction is satisfied, an operation specified by the operation code in the conditional execution instruction.
With the stated construction, the processor of the present invention uses an instruction set including conditional flag setting instructions and instructions which are executed when their conditions are satisfied, not including instructions which are executed when their conditions are not satisfied. Therefore, the instruction set includes only one type of instruction which is executed when its condition is satisfied for each operation.
A conventional processor uses ten types of conditional instructions for each operation and two types of instructions which are executed when their conditions are satisfied. As the number of operations of instructions which are executed when their conditions are satisfied increases, the processor of the present invention uses less types of the instructions.
Accordingly, hardware scale and cost of an instruction decoder can be reduced. Also, when the number of types of instructions are limited, the processor of the present invention can use conditional instructions for more operations. Therefore, when the processor of the present invention performs pipeline processing, branch hazards can be reduced.
Here, each of the first conditional flag setting instruction and the second conditional flag setting instruction may specify two comparison objects a and b, where the instruction set is assigned three types of first conditional flag setting instructions and three types of second conditional flag setting instructions, the first conditions of the first conditional flag setting instructions being a combination of the following conditions: 1. one out of xe2x80x9ca=bxe2x80x9d and xe2x80x9caxe2x89xa0bxe2x80x9d; 2. one out of xe2x80x9caxe2x89xa7bxe2x80x9d and xe2x80x9ca less than bxe2x80x9d; and 3. one out of xe2x80x9caxe2x89xa6bxe2x80x9d and xe2x80x9ca greater than bxe2x80x9d, the second conditions of the second conditional instructions being three mutually exclusive conditions for the three first conditions.
With the stated construction, the processor of the present invention uses six types of conditional flag setting instructions and the conditions of these instructions are three pairs of exclusive conditions. Therefore, without instructions which are executed when their conditions are not satisfied, the processor of the present invention can perform the same processing as a conventional processor.
Accordingly, the number of types of instructions can be reduced without sacrificing the performance of the processor of the present invention.
Here, the instruction set may be further assigned two types of first conditional flag setting instructions and two types of second conditional flag setting instructions, the first conditions of the first conditional flag setting instructions being a combination of the following conditions: 4. one out of xe2x80x9caxe2x89xa7bxe2x80x9d and xe2x80x9ca less than bxe2x80x9d; and 5. one out of xe2x80x9caxe2x89xa7bxe2x80x9d and xe2x80x9ca greater than bxe2x80x9d (where a and b of conditions 4 and 5 are compared with signs of a and b being taken into account), and the second conditions of the second conditional flag setting instructions being mutually exclusive with the first conditions.
With the stated construction, the processor of the present invention uses ten types of conditional flag setting instructions and the conditions of these instructions are five pairs of exclusive conditions. Therefore, without instructions which are executed when their conditions are not satisfied, the processor of the present invention can perform the same processing as a conventional processor.
Accordingly, the number of types of instructions can be reduced without sacrificing the performance of the processor of the present invention.
Here, an operation code included in a conditional execution instruction may be one of a transfer operation code, an arithmetic operation code, a logic operation code, and a branch operation code.
With the stated construction, the operation of each instruction which is executed when its condition is satisfied included in the instruction set of the processor of the present invention is a transfer operation, an arithmetic operation, a logic operation, or a branch operation.
Therefore, the processor of the present invention can use transfer instructions which are executed when their conditions are satisfied, arithmetic instructions which are executed when their conditions are satisfied, and logic instructions which are executed when their conditions are satisfied, and branch instructions which are executed when their conditions are satisfied. Accordingly, when the processor of the present invention performs pipeline processing, branch hazards can be reduced.
To achieve the above object, the instruction conversion apparatus of the present invention converts instruction sequences not including conditional instructions into instruction sequences including conditional instructions, each of the conditional instructions including a condition and an operation code and having a processor execute an operation specified by the operation code only if the condition is satisfied, and includes: an obtaining unit for obtaining an instruction sequence which does not include conditional instructions; an instruction sequence detection unit for detecting, out of the obtained instruction sequence, a conversion target instruction sequence which transfers different transfer objects to a same storage resource depending on whether a predetermined condition is satisfied; a judging unit for judging whether an instruction set of a specialized processor is assigned a conditional instruction including a same condition as the predetermined condition; and a conversion unit for converting, when a judgement result by the judging unit is affirmative, the conversion target instruction sequence into an instruction sequence including a conditional instruction including the predetermined condition and for interchanging, when the judgement result by the judging unit is negative, the transfer objects of the conversion target instruction sequence and converts the conversion target instruction sequence into an instruction sequence including a conditional instruction including a condition that is mutually exclusive with the predetermined condition.
With the stated construction, the instruction conversion apparatus of the present invention does not generate undecodable conditional instructions but decodable conditional instructions for the specialized processor.
Therefore, the instruction conversion apparatus of the present invention can reduce the number of types of conditional instructions without reducing total number of conditional instructions, so that the number of fields for including instructions and a code size can be reduced. Also, the number of types of conditional instructions decodable by the specialized processor can be reduced without sacrificing the performance of the specialized processor.
Accordingly, hardware scale of an instruction decoder of the specialized processor can be reduced. Also, when the number of types of instructions is limited, the specialized processor can use conditional instructions for more operations in comparison with a conventional processor. As a result, when the specialized processor performs pipeline processing, branch hazards can be reduced.
Here, the instruction set of the specialized processor may be assigned a conditional instruction including a condition that is mutually exclusive with a condition included in a conditional instruction judged as not assigned to the instruction set by the judging unit, and conditions included in conditional instructions for a same operation assigned to the instruction set are not mutually exclusive.
With the stated construction, the judging unit of the instruction conversion apparatus of the present invention judges that the specialized processor uses an instruction set including conditional instructions specifying only one out of a pair of exclusive conditions. Therefore, the instruction conversion apparatus of the present invention does not generate conditional instructions specifying the other of the pair of exclusive conditions.
Here, execution of a conditional instruction may be only possible after a comparison instruction, and the instruction set may be assigned three types of conditional instructions for each operation according to a relation between magnitudes of two comparison objects compared by the comparison instruction, the conditions of the three types of conditional instructions being: 1. one out of xe2x80x9ca=bxe2x80x9d and xe2x80x9caxe2x89xa0bxe2x80x9d; 2. one out of xe2x80x9caxe2x89xa7bxe2x80x9d and xe2x80x9ca less than bxe2x80x9d; and 3. one out of xe2x80x9caxe2x89xa6bxe2x80x9d and xe2x80x9ca greater than bxe2x80x9d.
With the stated construction, the judging unit of the instruction conversion apparatus of the present invention judges that the specialized processor can decode three types of conditional instructions for each operation. Therefore, the number of types of conditional instructions is reduced by half of six types of conditional instructions for a conventional processor.
Here, each of the transfer objects is one of a numerical value, a value indicated by a different storage resource, an operation result of a numerical value and a value indicated by the different storage resource, an operation result of numerical values, and an operation result of values indicated by the different storage resource.
With the stated construction, the operation specified by a conditional instruction is a transfer operation, an arithmetic operation, and a logic operation.
Therefore, the instruction conversion apparatus can generate conditional instructions for all of transfer instructions, arithmetic instructions, and logic instructions. Accordingly, when the specialized processor performs pipeline processing, branch hazards is reduced.
Here, the conversion target instruction sequence may consecutively include a conditional branch instruction for branching to a next instruction but two, a transfer instruction for transferring a transfer object to a storage resource, an unconditional branch instruction for branching to a next instruction but one, and a transfer instruction for transferring another transfer object to the storage resource.
With the stated construction, the instruction sequence detection unit detects this instruction sequence.
To achieve the above object, the instruction conversion apparatus of the present invention converts conditional instructions included in instruction sequences, each of the conditional instructions including a condition and an operation code and having a processor execute an operation specified by the operation code only if the condition is satisfied, and includes: an obtaining unit for obtaining an instruction sequence including conditional instructions; a conditional instruction detection unit for detecting a conditional instruction included in the obtained instruction sequence; a first judging unit for judging whether the detected conditional instruction is assigned to an instruction set of a specialized processor; a second judging unit for judging, when a judgement result by the first judging unit is negative, whether the obtained instruction sequence includes a conversion target instruction sequence which transfers different transfer objects to a same storage resource depending on whether a predetermined condition of the detected conditional instruction is satisfied; and a conversion unit for interchanging, when a judgement result by the second judging unit is affirmative, the transfer objects and converts the detected conditional instruction into a conditional instruction including a condition that is mutually exclusive with the predetermined condition.
With the stated construction, the instruction conversion apparatus of the present invention can converts undecodable conditional instructions into decodable conditional instructions for the specialized processor.
Therefore, the instruction conversion apparatus of the present invention can reduce the number of types of conditional instructions without reducing total number of conditional instructions, so that the number of fields for including instructions and a code size can be reduced. Also, the number of types of conditional instructions decodable by the specialized processor can be reduced without sacrificing the performance of the specialized processor.
Accordingly, hardware scale of an instruction decoder of the specialized processor can be reduced. Also, when the number of types of instructions is limited, the specialized processor can use conditional instructions for more operations. As a result, when the specialized processor performs pipeline processing, branch hazards can be reduced.
Here, the instruction set of the specialized processor may be assigned a conditional instruction including a condition being mutually exclusive with a condition included in a conditional instruction judged as not assigned to the instruction set by the first judging unit, and conditions included in conditional instructions for a same operation assigned to the instruction set are not mutually exclusive.
With the stated construction, the first judging unit of the instruction conversion apparatus of the present invention judges that the specialized processor uses an instruction set including conditional instructions specifying only one out of a pair of exclusive conditions. Therefore, the instruction conversion apparatus of the present invention does not generate conditional instructions specifying the other of the pair of exclusive conditions.
Here, the conversion target instruction sequence consecutively may include a comparison instruction for comparing two comparison objects, a transfer instruction for transferring a predetermined transfer object to a predetermined storage resource, and a conditional instruction for transferring a transfer object that differs from the predetermined transfer object to the predetermined storage resource only if a predetermined condition is satisfied.
With the stated construction, the instruction sequence detection unit detects this instruction sequence.
Here, the conversion unit may include: an inverse conversion unit for converting, when a judgement result by the second judging unit is negative, the instruction sequence including the detected conditional instruction into an instruction sequence not including the detected conditional instruction.
With the stated construction, even if a conditional instruction cannot be decoded by the specialized processor and cannot be converted into a conditional instruction which can be decoded by the specialized process, this conditional instruction is converted into an original instruction sequence.
Therefore, the instruction conversion apparatus of the present invention generates executable instruction sequences for the specialized processor.
To achieve the above object, the instruction conversion apparatus of the present invention converts an instruction sequence not including a conditional flag setting instruction and a conditional execution instruction into an instruction sequence including a conditional flag setting instruction and a conditional execution instruction, each conditional flag setting instruction including a condition, having a specialized processor judge whether the condition is satisfied, and having a conditional flag hold a judgement result as to whether the condition is satisfied, each conditional execution instruction including an operation code and having the specialized processor execute an operation specified by the operation code only if a condition of the conditional execution instruction is satisfied. The instruction conversion apparatus includes: an obtaining unit for obtaining an instruction sequence which does not include conditional flag setting instructions and conditional execution instructions; an instruction sequence detection unit for detecting, out of the obtained instruction sequence, a conversion target instruction sequence which transfers different transfer objects to a same storage resource depending on whether a predetermined condition is satisfied; and a conversion unit for converting the conversion target instruction sequence into an instruction sequence which includes a conditional flag setting instruction including the predetermined condition and a conditional execution instruction including an operation code which specifies an operation for transferring a transfer object to the storage resource when the predetermined condition is satisfied.
With the stated construction, the instruction conversion apparatus of the present invention generates decodable conditional flag setting instruction and decodable instructions which are executed when their conditions are satisfied for the specialized processor.
Therefore, the instruction conversion apparatus of the present invention can reduce the number of types of conditional instructions without reducing total number of conditional instructions, so that the number of fields for including instructions and a code size can be reduced. Also, the number of types of conditional instructions decodable by the specialized processor can be reduced without sacrificing the performance of the specialized processor.
Accordingly, hardware scale of an instruction decoder of the specialized processor can be reduced. Also, when the number of types of instructions is limited, the specialized processor can use conditional instructions for more operations. As a result, when the specialized processor performs pipeline processing, branch hazards can be reduced.
When the specialized processor uses instructions which are executed when their conditions are satisfied for 20 operations, for instance, it is enough to include in an instruction set 30 types of instructions including 10 types of conditional flag setting instruction and 20 types of instruction which are executed when their conditions are satisfied (one type of the instruction which is executed when its condition is satisfiedxc3x9720 operations).
Here, a condition of a conditional flag setting instruction which is convertible by the conversion unit may be mutually exclusive with a condition of another conditional flag setting instruction which is convertible by the conversion unit.
With the stated construction, during the generation of instructions which are executed when their conditions are not satisfied, it is enough for the instruction conversion apparatus of the present invention to generate conditional flag setting instruction specifying exclusive conditions and instructions which are executed when their conditions are satisfied. Therefore, the instruction set does not need to include instructions which are executed when their conditions are not satisfied.
Accordingly, instructions which are executed when their conditions are not satisfied can be eliminated without sacrificing the performance of the specialized processor.
Here, each conditional flag setting instruction may specify two comparison objects a and b, where the instruction set is assigned three types of first conditional flag setting instructions and three types of second conditional flag setting instructions, the first conditions of the first conditional flag setting instructions being a combination of the following conditions: 1. one out of xe2x80x9ca=bxe2x80x9d and xe2x80x9caxe2x89xa0bxe2x80x9d; 2. one out of xe2x80x9caxe2x89xa7bxe2x80x9d and xe2x80x9ca less than bxe2x80x9d; and 3. one out of xe2x80x9caxe2x89xa6bxe2x80x9d and xe2x80x9ca greater than bxe2x80x9d, the second conditions of the second conditional flag setting instructions being three mutually exclusive conditions for the three first conditions.
With the stated construction, the conversion unit of the instruction conversion apparatus of the present invention generates six types of conditional flag setting instruction. Each pair of the conditions of these instructions is in an exclusive relation. Therefore, even if an instruction set does not include instructions which are executed when their conditions are not satisfied, the same processing as a conventional processor can be performed.
Accordingly, the number of types of instructions can be reduced without sacrificing the performance of the specialized processor.
Here, the conversion target instruction sequence may consecutively include a comparison instruction for comparing two comparison objects, a conditional branch instruction for branching to a next instruction but two when a predetermined condition is satisfied, a transfer instruction for transferring a predetermined transfer object to a predetermined storage resource, an unconditional branch instruction for branching to a next instruction but one, and a transfer instruction for transferring a transfer object that differs from the predetermined transfer object to the predetermined storage resource.
With the stated construction, the instruction sequence detection unit detects this instruction sequence.
Here, the conversion target instruction sequence may consecutively include a comparison instruction for comparing two comparison objects, a transfer instruction for transferring a predetermined transfer object to a predetermined storage resource, and a conditional instruction for transferring a transfer object that differs from the predetermined transfer object to the predetermined storage resource only if a predetermined condition is satisfied.
With the stated construction, the instruction sequence detection unit detects this instruction sequence.
Here, the conversion target instruction sequence may consecutively include a comparison instruction for comparing two comparison objects, a conditional instruction for transferring a predetermined transfer object to a predetermined storage resource only if a predetermined condition is not satisfied, and a conditional instruction for transferring a transfer object that differs from the predetermined transfer object to the predetermined storage resource only if the predetermined condition is satisfied.
With the stated construction, the instruction sequence detection unit detects this instruction sequence.
To achieve the above object, the computer-readable recording medium of the present invention records an instruction conversion program for having a computer perform a method of converting instruction sequences not including conditional instructions into instruction sequences including conditional instructions, each of the conditional instructions including a condition and an operation code and having a processor execute an operation specified by the operation code only if the condition is satisfied. The program includes: an obtaining step for obtaining an instruction sequence which does not include conditional instructions; an instruction sequence detection step for detecting, out of the obtained instruction sequence, a conversion target instruction sequence which transfers different transfer objects to a same storage resource depending on whether a predetermined condition is satisfied; a judging step for judging whether an instruction set of a specialized processor is assigned a conditional instruction including a same condition as the predetermined condition; and a conversion step for converting, when a judgement result in the judging step is affirmative, the conversion target instruction sequence into an instruction sequence including a conditional instruction including the predetermined condition and for interchanging, when the judgement result in the judging step is negative, the transfer objects of the conversion target instruction sequence and converts the conversion target instruction sequence into an instruction sequence including a conditional instruction including a condition that is mutually exclusive with the predetermined condition.
With the stated steps, the instruction conversion program of the present invention does not generate undecodable conditional instructions but decodable conditional instructions for the specialized processor.
Therefore, the instruction conversion program of the present invention can reduce the number of types of conditional instructions without reducing total number of conditional instructions, so that the number of fields for including instructions and a code size can be reduced. Also, the number of types of conditional instructions decodable by the specialized processor can be reduced without sacrificing the performance of the specialized processor.
Accordingly, hardware scale of an instruction decoder of the specialized processor can be reduced. Also, when the number of types of instructions is limited, the specialized processor can use conditional instructions for more operations in comparison with a conventional processor. As a result, when the specialized processor performs pipeline processing, branch hazards can be reduced.
To achieve the above object, the computer-readable recording medium of the present invention records an instruction conversion program for having a computer perform a method of converting conditional instructions included in instruction sequences, each of the conditional instructions including a condition and an operation code and having a processor execute an operation specified by the operation code only if the condition is satisfied. The program includes: an obtaining step for obtaining an instruction sequence including conditional instructions; a conditional instruction detection step for detecting a conditional instruction included in the obtained instruction sequence; a first judging step for judging whether the detected conditional instruction is assigned to an instruction set of a specialized processor; a second judging step for judging, when a judgement result in the first judging step is negative, whether the obtained instruction sequence includes a conversion target instruction sequence which transfers different transfer objects to a same storage resource depending on whether a predetermined condition of the detected conditional instruction is satisfied; and a conversion step for interchanging, when a judgement result in the second judging step is affirmative, the transfer objects and converts the detected conditional instruction into a conditional instruction including a condition that is mutually exclusive with the predetermined condition.
With the stated steps, the instruction conversion program of the present invention can converts undecodable conditional instructions into decodable conditional instructions for the specialized processor.
Therefore, the instruction conversion program of the present invention can reduce the number of types of conditional instructions without reducing total number of conditional instructions, so that the number of fields for including instructions and a code size can be reduced. Also, the number of types of conditional instructions decodable by the specialized processor can be reduced without sacrificing the performance of the specialized processor.
Accordingly, hardware scale of an instruction decoder of the specialized processor can be reduced. Also, when the number of types of instructions is limited, the specialized processor can use conditional instructions for more operations. As a result, when the specialized processor performs pipeline processing, branch hazards can be reduced.
To achieve the above object, the computer-readable recording medium of the present invention records an instruction conversion program for having a computer perform a method of converting an instruction sequence not including a conditional flag setting instruction and a conditional execution instruction into an instruction sequence including a conditional flag setting instruction and a conditional execution instruction, each conditional flag setting instruction including a condition, having a specialized processor judge whether the condition is satisfied, and having a conditional flag hold a judgement result as to whether the condition is satisfied, each conditional execution instruction including an operation code and having the specialized processor execute an operation specified by the operation code only if a condition of the conditional execution instruction is satisfied. The program includes: an obtaining step for obtaining an instruction sequence which does not include conditional flag setting instructions and conditional execution instructions; an instruction sequence detection step for detecting, out of the obtained instruction sequence, a conversion target instruction sequence which transfers different transfer objects to a same storage resource depending on whether a predetermined condition is satisfied; and a conversion step for converting the conversion target instruction sequence into an instruction sequence which includes a conditional flag setting instruction including the predetermined condition and a conditional execution instruction including an operation code which specifies an operation for transferring a transfer object to the storage resource when the predetermined condition is satisfied.
With the stated steps, the instruction conversion program of the present invention generates decodable conditional flag setting instruction and decodable instructions which are executed when their conditions are satisfied for the specialized processor.
Therefore, the instruction conversion program of the present invention can reduce the number of types of conditional instructions without reducing total number of conditional instructions, so that the number of fields for including instructions and a code size can be reduced. Also, the number of types of conditional instructions decodable by the specialized processor can be reduced without sacrificing the performance of the specialized processor.
Accordingly, hardware scale of an instruction decoder of the specialized processor can be reduced. Also, when the number of types of instructions is limited, the specialized processor can use conditional instructions for more operations. As a result, when the specialized processor performs pipeline processing, branch hazards can be reduced.
When the specialized processor uses instructions which are executed when their conditions are satisfied for 20 operations, for instance, it is enough to include in an instruction set 30 types of instructions including 10 types of conditional flag setting instruction and 20 types of instruction which are executed when their conditions are satisfied (one type of the instruction which is executed when its condition is satisfiedxc3x9720 operations).
As described above, the present invention has great practical uses.